The present invention relates to digital signal processing systems, in general, and more particularly to a digital signal processing system including a programmable bulk memory comprising a plurality of memory sections independently controlled and simultaneously operative for transferring blocks or vectors of digital data words directly between selected memory sections and external data handling units while maintaining the corresponding variety of data handling throughput rates thereof without the need for input-output buffer type memories coupled therebetween.
Generally, a digital signal processing system includes a bulk memory for storage of large data files for use by at least one signal processing unit interfaced therewith. Usually, data is obtained from one or more input data sources in the form of blocks or vectors of digital data words. Because of the throughput rate differences between the data input sources and the bulk memory, certain buffer memory units, such as first-in-first-out memories, for example, may be coupled therebetween to collect and transfer the blocks of data to the bulk memory. Other input-output buffer memories may be coupled between the digital signal processors and the bulk memory to compensate for the exchange rate differences also existing therebetween.
In addition, the bulk memory may also distribute the processed data stored therein to various destination units also utilizing output buffer memories to accommodate the differences of throughput rates in the transfer of data words. Typically, a storage controller is included as part of the bulk memory for independently accessing or storing the blocks of data words under control of a programmed set of instructions. For a more detailed description of exemplary digital signal processing systems of this type, reference is hereby made to the U.S. Pat. Nos. 4,166,289 issued to John C. Murtha et al. on Aug. 28, 1979 and 3,812,470 issued to John C. Murtha et al. on May 21, 1974; and to the aforementioned referenced copending continuation application bearing Ser. No. 146,934 filed May 5, 1980 by John C. Murtha et al., all being assigned to the same assignee as the present application.
In view of that described hereabove, it appears that the digital signal processing systems of the type referred to above are adequate in their performance of certain specified operations. However, this does not mean that they may not be improved in order to enhance the effectiveness of their data transfer and processing operations. For example, while the input-output buffer memories appear to adequately provide a transfer mechanism which compensates for the varying throughput rates between the bulk memory and the data handling units interfacing therewith, they also provide additional hardware for the temporary buffer storage of the blocks of data words being transferred and for the control logic required for the data word transfer operations associated therewith. A more detailed description of input-output buffer memories of this type, especially for the case where independent operation is desired, is outlined in the aforementioned copending continuation application Ser. No. 146,934.
Another avenue of improvement may be connected with the storage and accessing operations of the data files in the bulk memory of a digital signal processing system. Present digital signal processing systems, such as the one described in the aforementioned U.S. Pat. Nos. 4,166,289 and 3,812,470, for example, provide for the transfer of only one block of data words at a time between the bulk memory and the various data handling units interfaced therewith. In other words, concurrent operations of collecting and supplying digital data words to and from the bulk memory, respectively, does not appear to be facilitated by the processing system architecture thereof. What is provided, however, is a complex priority and interrupt structure to allow for the transfers of more important information over that of lesser importance. This of course increases the complexities of the bulk memory storage controller.
In still another area, it is understood that in some signal processing systems the blocks of digital data words are processed in a non-sequential manner. In these instances, the blocks of data words are stored and accessed to expedite the throughput rate in connection with this non-sequential processing requirement. For example, in some radar systems which detect moving targets, digitized video echo signals in the form of blocks or vectors of data words are transferred to and stored in the bulk memory in accordance with a broad spectrum of ranges or range cells. However, in the processing of these vectors, a vector arithmetic processor, for example, many process the information of one range cell over a period of time. Thus, the stored data words must be sequentially accessed to accommodate the processing operations in order to detect target motion in a given range cell. In the radar art, this sequencing is more commonly referred to as corner turn sequencing.
To further complicate matters, the bulk memory because of the requirements of higher density memory parts generally has a slower data transfer rate than that of the signal processor. For this reason, time multiplexing of prespecified memory cells is, at times, utilized to compensate for the differences in transfer rates. In the instances where both time multiplexing and corner turn sequencing are both desired, the data vectors should be stored and accessed to facilitate compliance with the time multiplexing operations in order to permit expeditious data transfer between the bulk memory and the external data handling units, especially that of a high speed signal processor.
While only a few of the improvement aspects of a digital signal processing system especially in the area of the bulk memory and storage controller have been described hereabove, they are sufficient to demonstrate the improvement potential in such systems. Furthermore, while the inventive aspects described herebelow in a preferred embodiment form are directed primarily to the bulk memory and the control logic associated therewith, it is understood that improvements in these areas will additionally improve the effectiveness of an overall digital signal processing system. Accordingly, the overall improvements to the digital processing system resulting from the inventive aspects will become more fully understood and appreciated from the description of the preferred embodiment found herebelow.